This invention relates to memory systems. More particularly, it is concerned with random access memory (RAM) systems employing bipolar transistors.
Random access memory systems employing an array of memory elements arranged in an electrical matrix of rows and columns are well-known. One type of system employing memory elements which utilize two bipolar transistors in a bistable circuit is described in an article entitled "A 25-ns Read Access Bipolar 1Kbit TTL RAM" by Mayumi et al in the IEEE Journal of Solid-State Circuits, October 1974. Circuits of the type described are widely used in integrated circuit memory systems. Each of the memory elements has two stable operating states, in each state one of the transistors is on and the other is off. Each row of memory elements is designated as storing a word and is either in a selected condition to permit the reading out or writing in of data or remains in a standby condition. The voltage level on a word select line connected to the memory elements of a row either selects the row to be in the read-write mode or causes the row to be in the standby mode. Each column of memory elements stores a bit of each word. Bit lines are connected to each of the memory elements of a column for reading out or writing in data to the memory elements of the column. An individual memory element of the array is selected by selection of the appropriate row and column.
When a memory element is in the standby mode as determined by the voltage level on its associated word select line, current flow through the on transistor does not affect the associated bit lines nor do signals on the bit lines affect the memory element. A memory element is selected, or placed in the read/write mode, by an appropriate voltage level applied to the associated word select line. In order to write data into a memory element by changing its operating state a writing current is passed through the off transistor of the memory element to turn the off transistor on. The wiriting current must be greater than the holding current flowing through the on transistor. Positive feedback causes the transistors to reverse operating states. While the transistors are in the process of changing operating states, voltages within the memory element change tending to reduce the flow of holding current therethrough. Usually the blocked holding current is diverted to flow through any of the memory elements of the row which are not undergoing a change of state. Thus, the switching action takes place rapidly with no interference caused by the blocked holding current.
In many applications employing memory systems of the foregoing type it is desired to write data into all the memory elements of a selected row at the same time. If one or more of the memory elements of the row is not being switched to the opposite state, the blocked holding current from the memory elements being switched passes through those memory elements of the row which are not being switched. If all of the memory elements of the row are being switched to the opposite state simultaneously, however, alternative paths for the blocked holding current are not available. The resulting voltage levels within the memory elements have an adverse effect on their switching speeds thus reducing the rate at which the memory system can be operated reliably.